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  • Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design)

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Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design)

by Ivan Sutherland (Author), Robert F. Sproull (Author), David Harris (Author) Format: Paperback
3.3 out of 5 stars (7)
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Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.

The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.

  • Explains the method and how to apply it in two practically focused chapters.
  • Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
  • Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
  • Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.
  • Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.
  • Presents a complete derivation of the method-so you see how and why it works.

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  1. ISBN-10
    9781558605572
  2. ISBN-13
    978-1558605572
  3. Edition
    1st
  4. Publisher
    Morgan Kaufmann
  5. Publication date
    February 16, 1999
  6. Part of series
    The Morgan Kaufmann Series in Computer Architecture and Design
  7. Language
    English
  8. Dimensions
    7.39 x 0.41 x 9.19 inches
  9. Print length
    256 pages
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Editorial Reviews

From the Back Cover

Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.

The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.

Features

  • Explains the method and how to apply it in two practically focused chapters.
  • Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.
  • Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.
  • Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.
  • Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.
  • Presents a complete derivation of the method-so you see how and why it works.

About the Author

Ivan E. Sutherland, a vice president and fellow at Sun Microsystems, received the Turing Award and the Von Neumann Medal for his pioneering contributions in the fields of computer graphics and microelectronic design.

Robert F. Sproull is an internationally noted expert on the design of graphics hardware and software. He too is a vice president and fellow at Sun.

David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.

Product details

  • ASIN ‏ : ‎ 1558605576
  • Publisher ‏ : ‎ Morgan Kaufmann
  • Publication date ‏ : ‎ February 16, 1999
  • Edition ‏ : ‎ 1st
  • Language ‏ : ‎ English
  • Print length ‏ : ‎ 256 pages
  • ISBN-10 ‏ : ‎ 9781558605572
  • ISBN-13 ‏ : ‎ 978-1558605572
  • Item Weight ‏ : ‎ 1 pounds
  • Dimensions ‏ : ‎ 7.39 x 0.41 x 9.19 inches
  • Part of series ‏ : ‎ The Morgan Kaufmann Series in Computer Architecture and Design
  • Best Sellers Rank: #617,440 in Books (See Top 100 in Books)
  • Customer Reviews:
    3.3 out of 5 stars (7)

About the authors

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  1. David Money Harris

    David Money Harris

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    David Money Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College and the author of terrific engineering textbooks and hiking guidebooks. He received his Ph.D. from Stanford University in Electrical Engineering and his M.Eng. and S.B. degrees in EECS and Mathematics from the Massachusetts Institute of Technology. He has designed microprocessors at Intel Corporation, Hewlett Packard, Sun Microsystems, and Broadcom, and his passion for chips is reflected in his books on the subject. He began his hiking adventures as a wee tot on his father's back and has been exploring the mountains and deserts ever since. Now, his own three boys are frequent companions on these trips.

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  2. David Harris

    David Harris

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  3. Ivan Edward Sutherland

    Ivan Edward Sutherland

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Customer reviews

3.3 out of 5 stars
7 global ratings
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Top reviews from the United States

  • SK
    5 out of 5 stars
    Had to buy this book
    Reviewed in the United States on March 20, 2012
    Format: Paperback
    Verified Purchase
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    I am currently doing a Masters degree in VLSI, and although this is not on the required book list, after trying endless parametric simulations of critical path device sizes, and trying to find the minimum delay, I found Logical efforts to be a much more elegant approach to doing that. Although some other books discuss it in minimal detail, there is no mention of if the same can be extended to other logic families other than Static CMOS. I went through a few pages of the book, and decide it to be a must buy. I also thought it was pretty cheap for 60$. Unfortunately, the book is pretty small - it's not like a 500 page book which I was expecting it to be.

    I am yet to read through the whole book (which I plan to - very soon), and shall update this review once I am done with that. But I am expecting it to be worth the every cent I paid for it.

    One person found this helpful
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  • DL19
    5 out of 5 stars
    It's a pretty incredible book
    Reviewed in the United States on March 15, 2021
    Format: Kindle
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    It's pretty incredible most VLSI or CMOS only present very basic logical effort section. I never seen a book that presented the subject so clearly and waste no time either. Of course the guys who invented logical efforts method are the guys who wrote this book. ;)

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  • Joy
    4 out of 5 stars
    Logical Effort: Designing Fast CMOS Circuits (The Morgan Kaufmann Series in Computer Architecture and Design)
    Reviewed in the United States on November 4, 2006
    Format: Paperback
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    This book was really easy to read and explained the concepts well in some areas. Part of this is because my professor followed this book closely and synced it with his lectures. There were some areas that were very difficult to fully grasp without his lectures. One thing the book failed to do was fully describe assymetric sizing. They only described two input gates but never went into three input gates which is a little more tricky. There are other topics where more information would have been helpful.

    2 people found this helpful
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  • Mika Nystroem
    4 out of 5 stars
    A very good book for designers or advanced students
    Reviewed in the United States on September 25, 1999
    Format: Paperback
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    This book is a long overdue explanation of the "Logical Effort" approach to MOS circuit design invented by two of the authors, Sutherland and Sproull, in the late 80's. The technique presented is complete and powerful, and this book should be required reading for all persons involved in high-performance or low-power MOS digital design. Nevertheless, I would not recommend it for beginners without some of what the authors call "instruction from veteran designers." The main shortcoming of the book is a lack of organization---important points are sometimes made in seemingly unrelated sections, and the sections themselves do not always appear to follow the most logical arrangement---and it could stand a more thorough editing job to clean up some of the presentation. Sometimes, I felt that information that was presented in charts would have been much more powerful in graph form. A few of the graphs in the book are misleading (arbitrary scales and unmarked breaks in scales), and some of the mathematical terminology is imprecise. The fact that the authors picked, somewhat arbitrarily, a new definition of the technology delay parameter tau (instead of sticking to the definition established by Mead & Conway in their 1980 book) is annoying. Aspiring asynchronous designers should be cautioned that the two designs for an n-input Muller C-element contrasted in Section 11.2 are logically different. A section contrasting the uses of the logical effort method in synchronous and asynchronous designs would also be welcome. All in all, however, the book is very readable, and it is easy to follow. It would be effective as a textbook, and it is a most welcome addition to my library because it treats a difficult and important topic better and in more detail than any other published work.

    16 people found this helpful
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  • Pradeep Kanapathipillai
    5 out of 5 stars
    Well written, and fun to read.
    Reviewed in the United States on January 17, 2009
    Format: Paperback
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    Theory on the sizing of CMOS gates, written in a fun and readable manner by David Harris (from Harvey Mudd, prev at Stanford/MIT). I found it useful when I was getting started with designing circuits for custom microprocessors, because it helps to know the limits of speedup that transistor sizing can give, and Logical-Effort is a very useful framework to understand the tradeoffs.

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