What's Changed

• [alu] optimize set-on-less-than timing by @ekigwana in #1635
• [serial IO] use asynchronous bus read by @stnolting in #1638
• [io] implement async bus read access for further IO modules by @stnolting in #1640
• [ocd,gptmr,pwm] further area optimizations by @stnolting in #1641
• [clint] area optimizations by @stnolting in #1642
• 🐛 [axi bridge] full rework; add data buffering to handle back pressure by @stnolting in #1645
• minor rtl edits and cleanups by @stnolting in #1647
• test: add GPIO input loopback verification to processor_check by @Abolfazl-Azad in #1643
• [rtl] code cleanups and restructuring; extend Verilog flow by @stnolting in #1649
• sw/floating_point_test: fix unreachable special values and use signaling NaN by @Abolfazl-Azad in #1644
• [docs] fix small mistakes by @Gaweringo in #1650
• Bus and AMO improvements by @stnolting in #1651

New Contributors

• @Abolfazl-Azad made their first contribution in #1643
• @Gaweringo made their first contribution in #1650

Full Changelog: v1.13.5...v1.13.6

What's Changed

• [prim] declare FIFO/SPRAM memory arrays per generate-branch to fix RAM extraction on Verific-based synthesis tools by @CodeWarrior1241 in #1623
• [bitmanip] simplify register enables by @ekigwana in #1626
• Normalize bus/list array ranges to downto (ARY_MS_DRNG) by @john-kearney in #1622
• minor rtl edits and optimizations by @stnolting in #1624
• Fix typo in README about GHDL by @oof289 in #1627
• [cpu] generalize fast multiplier pipeline by @ekigwana in #1625
• Add a new function to the UART for a transmission with a newline by @Kampi in #1629
• [cpu] minor timing optimizations and cleanups by @stnolting in #1630
• Rework IP/module wrappers by @stnolting in #1631
• Convert remaining list arrays to downto (named-association aggregates) by @john-kearney in #1632
• 🐛 fix permanent CPU stall when accessing unmapped addresses (if XBUS is disabled) by @stnolting in #1634

New Contributors

• @ekigwana made their first contribution in #1626
• @john-kearney made their first contribution in #1622
• @oof289 made their first contribution in #1627
• @Kampi made their first contribution in #1629

Full Changelog: v1.13.4...v1.13.5

What's Changed

• 🐛 [pmp] fix pmpaddr*[31:30] - must be read-only and zero by @stnolting in #1605
• [rtl] minor updates und cleanups; simpplify CFS bus interface by @stnolting in #1606
• [cpu] remove reset from data path registers by @stnolting in #1609
• [rtl] use a single file-list file only by @stnolting in #1611
• [RVFI] extend order to 64-bit by @stnolting in #1612
• [regfile] optimizations and cleanups by @stnolting in #1613
• minor rtl cleanups and optimizations by @stnolting in #1614
• [instret counter] only increment for actually retired instructions by @stnolting in #1615
• [ci] build documentation: install tools natively by @stnolting in #1619
• [SoC] remove reset from registers where it is not strictly necessary by @stnolting in #1620
• [cpu] minor updates, optimizations and RV-compliance fixes by @stnolting in #1621

Full Changelog: v1.13.3...v1.13.4

What's Changed

• [docs] fix asciidoctor SVG issues by @stnolting in #1578
• [docs] add tip about vendor JTAG primitives by @NikLeberg in #1586
• fix(trace): align mem signals to RVFI monitor conventions by @gav-ai in #1585
• [zimop + zfinx] fix illegal instruction detection loopholes by @stnolting in #1590
• [rtl] minor edits and cleanups by @stnolting in #1594
• [zfinx] fix further illegal instruction detection loopholes by @stnolting in #1595
• ✨ add support for RISC-V Zcmop ISA extension (compressed may-be-operations) by @stnolting in #1596
• fix(trace): byte-exact address and LSb-normalized memory signals for RVFI conventions by @gav-ai in #1597
• ✨ add new module: Serial Memory Controller (SMC) by @stnolting in #1599
• Bootloader updates by @stnolting in #1601
• [vhdl] major coding style edits by @stnolting in #1602
• [cpu] Add optional CPU_FAST_MUL_REG generic for the fast multiplier by @CodeWarrior1241 in #1603

New Contributors

• @gav-ai made their first contribution in #1585
• @CodeWarrior1241 made their first contribution in #1603

Full Changelog: v1.13.2...v1.13.3

What's Changed

• 🐛 [Zalrsc] rework/fix reservation station and SC operation by @stnolting in #1556
• [slink] Assert ready signal only when enabled by @tkundrat in #1558
• Add option to configure uncached address space by @stnolting in #1561
• [sw/example] fixup twi demo SDL & SCL signal sense by @NikLeberg in #1564
• minor rtl edits and cleanups by @stnolting in #1565
• [docs] remove references folder by @stnolting in #1567
• 🐛 minor rtl fixes by @stnolting in #1568
• ⚠️ rework HPM counter events by @stnolting in #1569
• minor RTL edits and optimizations by @stnolting in #1570
• ⚠️ rework f-file format by @stnolting in #1573
• close RVC illegal instruction decoding loophole; shrink bootloader image size by @stnolting in #1574
• remove mhpmevent*h CSRs by @stnolting in #1575

New Contributors

• @tkundrat made their first contribution in #1558

Full Changelog: v1.13.1...v1.13.2

What's Changed

• Two write-back D-cache correctness fixes (fence.i + AMO bypass) by @14sea in #1540
• [image_gen] Pass a flattened ELF binary instead of parsing the ELF itself by @stnolting in #1541
• ⚠️ [cpu] rework trap CSRs (mcause, mtval, mtinst) by @stnolting in #1542
• [rtl] minor fixes, edits and cleanups (PMP, TWD, bus) by @stnolting in #1543
• Rework on-chip debugger by @stnolting in #1544
• ✨ [sim] add JTAG/DMI tests to testbench by @stnolting in #1545
• ✨ [Zihpm] add support for all 29 hardware performance monitors by @stnolting in #1546
• 🐛 [pmp] fix reserved permissions and address/mask storage by @stnolting in #1549
• ✨ add support for RISC-V Zbc ISA extension by @stnolting in #1550
• ✨ add support for time[h] CSRs by @stnolting in #1551
• remove riscv-arch-test folder and submodule by @stnolting in #1552
• [trace] add RVC trace logging by @stnolting in #1553

Full Changelog: v1.13.0...v1.13.1

What's Changed

• ✨ [cache] add write-back & write-allocate policies by @stnolting in #1513
• [sw/example] remove dhrystone by @stnolting in #1522
• 🧪 rework intrinsics (use .insn) by @stnolting in #1523
• ⚠️ simplify CFU interface by @stnolting in #1524
• add NEORV32-specific mxisah CSR by @stnolting in #1527
• 🐛 [bootloader] fix checksum computation by @stnolting in #1528
• Minor rtl fixes, edits and cleanups by @stnolting in #1531
• [uart] reset RX overflow flag on CTRL read by @stnolting in #1533
• Minor rtl (corner case) fixes and logic optimizations by @stnolting in #1534
• Rework C ISA extension's decompressor by @stnolting in #1537
• crt0 and linkerscript optimizations by @stnolting in #1538

Full Changelog: v1.12.9...v1.13.0

What's Changed

• Use macros for memory-mapped register bitmaks operations by @stnolting in #1497
• [twd] extend interrupts by @stnolting in #1498
• ⚠️ [twd] map to FIRQ channel 4 by @stnolting in #1499
• Optimize cache module by @stnolting in #1500
• Bump actions/upload-artifact from 6 to 7 by @dependabot[bot] in #1501
• Bump actions/download-artifact from 7 to 8 by @dependabot[bot] in #1502
• Minor rtl edits by @stnolting in #1503
• 🧪 Rework image generator: use ELF as input by @stnolting in #1504
• [bootloader] add flexible executable base address by @stnolting in #1505
• [twd] remove twd_scl_o signal by @stnolting in #1506
• 🐛 fix GPTMR half-word access to PRSC register by @stnolting in #1509
• [bootloader] add 2 new UART config options by @stnolting in #1510
• [sw/lib] replace deprectated RISC-V GCC macros by @stnolting in #1511
• [sw/lib] replace elf with libelf if on macOS by @urbanij in #1512
• 🐛 [image_gen] fix COE, MEM & MIF output by @stnolting in #1514
• [makefile] allow override of build result path; allow help extension by @wwwweb in #1516
• [makefile] try to determine host OS/platform by @stnolting in #1515
• [gpio] add optional IO direction control by @stnolting in #1517
• [trng] add TRNG architecture configuration generics and ⚠️ rework control register layout by @stnolting in #1518
• fix(bus): SC.W returns 0 on success instead of stale memory data by @14sea in #1520

New Contributors

• @urbanij made their first contribution in #1512
• @wwwweb made their first contribution in #1516
• @14sea made their first contribution in #1520

Full Changelog: v1.12.8...v1.12.9

What's Changed

• [svd] add fields to UART_DATA by @kurtjd in #1475
• [rtl] renanme bootloader ROM module by @stnolting in #1477
• 🐛 [cpu] fix csrr[r/c][i] instructions by @stnolting in #1479
• ✨ encapsulate memory components by @stnolting in #1481
• ⚠️ rework memory image files by @stnolting in #1482
• ✨ Add replace-by-Verilog example by @stnolting in #1483
• Rework/fix in-console executable upload via UART by @stnolting in #1484
• [sdi] Update docs and svd by @kurtjd in #1485
• 🐛 fix enabling of Zbkx ISA extension by @stnolting in #1486
• [sdi] Fix svd and docs typos by @kurtjd in #1488
• ⚠️ rename Zxcfu ISA extension by @stnolting in #1487
• minor rtl cleanups; improve timing of bus_switch module by @stnolting in #1489
• [top] add option to override default IMEM & DMEM base addresses by @stnolting in #1492
• ⚠️ [top] machine time IRQ typo fix by @stnolting in #1494

Full Changelog: v1.12.7...v1.12.8

What's Changed

• rtl edits, cleanups and optimizations by @stnolting in #1462
• [hpm] rework HPM events by @stnolting in #1463
• ✨ add support for RISC-V Smcntrpmf ISA extension (counter privilege-mode filtering) by @stnolting in #1464
• Add description to TOPCMP in svd by @kurtjd in #1466
• minor CPU cleanups and optimizations by @stnolting in #1465
• minor rtl edits by @stnolting in #1467
• Add Rust support to user guide by @kurtjd in #1469
• 🐛 fix bus timeout issue; minor rtl edits by @stnolting in #1470
• Relax cache size configuration constraints by @stnolting in #1471
• ⚠️ Rename ALU co-processor modules by @stnolting in #1472
• Make minor UART doc fixes by @kurtjd in #1473
• Minor RTL cleanups and optimizations by @stnolting in #1474

New Contributors

• @kurtjd made their first contribution in #1466

Full Changelog: v1.12.6...v1.12.7