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cgen: fix riscv64 closure - #24315
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Important note: At first I wanted to add tests in this commit, but then decided against it. I'll make a separate PR because I still need to touch GitHub CI too.
Happy reading.
This is an important
first PRfrom a future series that will fix closure on all broken architectures.Future PRs must and will reference it.
From the very first day when I dove into the wonderful world of assembly and closure implementations on different architectures, it was clear that they all differ. And one half is correct, while the other half is incorrect.
If you take a quick glance at all architectures, you'll easily see the key distinguishing feature - the use of 1 floating point register.
It remains to find or create a test that will show there is a problem. This turned out to be not so simple because you need to consider 4 (!) points simultaneously, where each combination is unique - architectures + implementation + compiler + registers.
Current
riscv64implementation:The author waits and hopes that between calls of two subroutines, the value in register
t6that is important for operation will be waiting for him.This is assembler for call __CLOSURE_GET_DATA from
gcc:The author saw that gcc doesn't use other registers and self-confidently uses
t6.clangreuses out temp register (clang 17-19):Now it's clear why this stub is placed in the important test
v/tests/fns/closure_generator_test.vto prevent crashing onclang. :) BTWarm64closures are seems broken too.The new implementation simply uses a floating point temporary register instead of a general-purpose temporary register, as in other architectures. There's nowhere else to store it, and the stack frame is not available to us.
GitHub CIwon't break for now, I'm not touchingtestsyet too.v/tests - OKwith gcc and clang.all closures - OKwith gcc and clang.