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cgen: fix riscv32 closure - #24355

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spytheman merged 1 commit into
vlang:masterfrom
tankf33der:riscv32
Apr 29, 2025
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spytheman merged 1 commit into
vlang:masterfrom
tankf33der:riscv32

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@tankf33der

@tankf33der tankf33der commented Apr 29, 2025 •

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I managed to set up my riscv32 in qemu and fix the closure

Highlights:

  • using a floating register
  • now all architectures use a floating register
  • the same order of lines as in riscv64
  • supporting any number of arguments in closure
  • verified in gcc14 and clang19
  • verified personally

@huly-for-github

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Connected to Hulyยฎ: V_0.6-22731

@spytheman spytheman left a comment

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Excellent work.
Thank you ๐Ÿ™‡๐Ÿปโ€โ™‚๏ธ.

@spytheman
spytheman merged commit ead4d90 into vlang:master Apr 29, 2025
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2 participants