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hyqneuron edited this page Mar 22, 2015 · 1 revision

This is a page where all other wiki pages of this project are listed and briefly described.


Overview

  • Home: Brief introduction to the project, current development state and Other related information.
  • Plan: This page deacribes the planned stages of the project. It also includes a timeline of the short-term objectives.
  • Updates: I know a few people are checking this site regularly, so I created this page so that you can know if anything has happened.

Stage 1, Assembler

Using asfermi

  • Features: A list of features that are supported/to be supported. The meaning of various state numbers are also explained here.
  • Usage: A page describing the command-line usage of asfermi.
  • SourceFormat: A specification of the format of source code that can be assembled.
  • CodeExample: A page with some examples showing how the input file of asfermi would look like.
  • KnownIssues: A list of known issues and other things that users of asfermi should take note of.
  • Instructions: A list of instructions that are supported/ to be supported.
  • Directives: A list of directives that are supported/to be supported.

Development related

  • Design: This page describes the framework under which the assembler is written.
  • HowToStart: This page lists the procedures of opcode probing
  • OpcodeToDo: A list of instructions to be probed soon.
  • Utilities A page describing the utilities made for the purpose of this project.

Fermi ISA

  • Opcode: A page describing the opcode format of the Fermi opcode.
  • nanb: A page with instruction names and their corresponding identifier bits.
  • OpcodeExecution: Opcode and instruction description for execution control instructions.
  • OpcodeDataMovement: Opcode and instruction description for data movement instructions.
  • OpcodeFloat: Opcode and instruction description for floating point number operation instructions.
  • OpcodeInteger: Opcode and instruction description for integer operation instructions.
  • OpcodeLogic: Opcode and instruction description for logic and shift instructions.
  • OpcodeConversion: Opcode and instruction description for conversion instructions.
  • OpcodeMiscellaneous: Opcode and instruction description for miscellaneous instructions.

Stage 2, Microbenchmarking

Test Sets

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